This guide assumes that you have finished all the steps in my previous post, Setting Up a RISC-V Security Testing Environment and have managed to generate a basic binary that simulates a RISC-V Rocket core using Verilator. Once Chipyard is basically up and running, you should have a chipyard folder that looks more or less […]
Monthly Archives: January 2020
Chipyard: Setting up a RISC-V security testing environment
My master’s thesis work has been in RISC-V security, a topic that has gained substantial relevance following major flaws discovered in popular (but very proprietary) CPU cores manufactured by companies like Intel, ARM, and AMD. An advantage to researchers interested in investigating micro architecture security is that RISC-V cores are completely open source, available to […]